How To: Simulate Mixed Language Designs
DSim Cloud fully supports mixed language designs in VHDL, Verilog, and SystemVerilog. There are different methods to compile and run your design, depending on the following:
- if VHDL is used, or the design is purely Verilog / SystemVerilog
- you want to compile once, run multiple times
- your preference for the 3 stages of simulation (Analyze, Elaborate, Run)
Commands
mdc dvhcom
is required to analyze any VHDL files
mdc dvlcom
is used to analyze any Verilog / SystemVerilog files
mdc dsim -a '-genimage ...'
is used to elaborate the design after the files have been analyzed
mdc dsim -a '-image ...'
is used to run the image after the design has been elaborated
mdc dsim -a '-F filelist.txt ...'
is used to analyze, elaborate, and run designs that are purely Verilog / SystemVerilog
Methods
1. 1-step Method: Analyze, Elaborate, and Run in one step.
This method is applicable if both are true:
- the design is purely Verilog / SystemVerilog
- you want to compile everything on every run (compile once, run once)
Command:
mdc dsim -a '<design files> <options>'
Examples:
mdc dsim -a '-F filelist.txt +acc+b -waves waves.vcd' mdc dsim -a 'my_dut.v my_ip.v my_tb.sv -timescale 1ns/1ps +acc+b -waves waves.vcd'
2. 2-step Method: Analyze and Elaborate in one step, Run in a second step.
This method is applicable if both are true:
- the design is purely Verilog / SystemVerilog
- you want to compile once, run multiple times
Commands:
mdc dsim -a '-genimage <image> <design files> <elaboration options>' mdc dsim -a '-image <image> <run options>'</run>
Example:
mdc dsim -a '-genimage myimage -F filelist.txt +acc+b' mdc dsim -a '-image myimage -waves waves.vcd'
3. 3-step Method: Analyze, Elaborate and Run in 3 separate steps.
This method is applicable if either are true:
- the design has VHDL and Verilog / SystemVerilog
- you want to compile once, run multiple times
Commands:
mdc dvhcom -a '<vhdl design files>' mdc dvlcom -a '<verilog or SystemVerilog files>' mdc dsim -a '-genimage <image> -top <library>.<module> <elaboration options>' mdc dsim -a '-image <image> <run options>'
Example:
mdc dvhcom -a '-F filelist_VHDL.txt' mdc dvlcom -a '-F filelist_SV.txt' mdc dsim -a '-genimage myimage -top work.carry_lookahead_adder_tb +acc+b' mdc dsim -a '-image myimage -waves waves.vcd'
Example
The carry_lookahead_adder example from the Walkthrough Tutorial has folders for VHDL, SystemVerilog, and VHDL_SystemVerilog implementations of the same design. Open /sim/readme.txt under these folders to see how to simulate the design according to the language(s) and methods described above.