How To: Simulate a Design with GOWIN IP
This How To guide is intended to be used by GOWIN customers to simulate their FPGA designs with GOWIN IP via Metrics DSim Cloud. It provides a generic procedure that can be applied to all such designs. The procedure gives recommended best practices without limiting the user's flexibility on workflow. There is a GOWIN Reference Design called Gowin_I2C_Master_refDesign which can be downloaded here. It can be examined while going through this guide for a better understanding of the procedure.
- Have a working installation of GOWIN EDA on your local machine.
- Successfully compile your design in GOWIN EDA.
- Complete the DSim Cloud Tutorial.
- Understand how to run a simulation in DSim - Verilog and/or VHDL, as applicable to your design.
- Review considerations for choosing the DSim Cloud local workspace.
- Understand how to use libraries in DSim.
- Understand how to use DSim Cloud CLI Tool simulator commands.
1. Prepare your local workspace
Ensure that all files needed to simulate your design are under your local workspace. These files include all design, testbench, memory initialization, source code for generated IP blocks, and all source code for the IP that the generated IP blocks depend on (eg. prim_sim.v). For example, your local workspace would be the GOWIN IP Reference Design folder Gowin_<design>_RefDesign. For the purpose of this guide, we will call this workspace origin directory my_project.
Create a folder under my_project called mdc where you will simulate your design with DSim Cloud. For example, you can create it as my_project/simulation/mdc. Copy all your memory initialization files (*.mif) to this folder. *mif files are not compiled but must reside in the same folder where you run your DSim Cloud simulation.
If any source code for an IP block is encrypted, you must instead provide the simulation model file (eg. i2c_master.vo instead of i2c_master.v). The simulation model file can be generated in GOWIN FPGA Designer as follows:
1. Under the Process tab, right-click Place & Route.
2. Click Configuration.
3. Under Place & Route, click General.
4. Double-click the Value column in the Generate Post-PnR Simulation Model File row.
5. Change the Value to True.
6. Click OK.
7. Rerun the Place & Route step in the Process tab.
8. Find the generated .vo file in the same folder as the encrypted .v file.
2. Create a compile list
For all the files required for compilation and simulation, you must know their language type, the library into which they should be compiled, and their source file location. For VHDL files, the order of compilation must be known. If desired, you can create a list of all files needed to compile and simulate the design, to keep track of this information. For example, under my_project:
*VHDL = VHDL-1993 unless otherwise noted
You can extract some of this information by opening your design's GOWIN project file, *.gprj, in a text editor.
3. Create a compile script or list of DSim Cloud commands
There are many ways to compile and simulate your design with the DSim simulator, contained within the DSim Cloud platform. Basically, you need to wrap the DSim command options to analyze, elaborate, and run your design, in single quotes so that the DSim command is executed on the remote compute.
Both IP and design files must be compiled into the appropriate libraries with DSim Cloud commands. The commands are different for Verilog / SystemVerilog files and VHDL files.
Verilog / SystemVerilog
mdc dvlcom -a '-lib <library_name> <path>/<file_name>.v'
mdc dvlcom -a '-lib sim_lib ./ip/sim/prim_sim.v' mdc dvlcom -a '-lib ip_lib -F ip_filelist.txt'
mdc dvhcom -a '-vhdl93 -lib <library_name> <path>/<file_name>.vhd'
mdc dvhcom -a '-vhdl2008 -lib work ./src/hdl/my_dut.vhd'
Depending on the complexity of your design, and your familiarity with scripting, you can put all these DSim Cloud commands together in a compile script and run the script with DSim Cloud. The script runs on your local compute and makes calls to DSim through the DSim Cloud CLI.
4. Simulate your design in DSim Cloud
1. Initialize a DSim Cloud workspace in your workspace origin directory my_project from section 1 of the Procedure.
2. Navigate to the my_project/simulation/mdc folder where you will run your simulation.
3. If your design requires VHDL IEEE libraries, set up the precompiled IEEE libraries in DSim Cloud.
4. Compile all the files into their appropriate libraries using the methods in section 3.
5. Elaborate your design. For example:
mdc dsim -a '-genimage image -top test_lib.my_tb +acc+b'
6. Run your design. For example:
mdc dsim -a '-image image -waves waves.mxd -wave-scope-specs wave.list'
7. You can view waveforms and/or download the DSim log to debug your simulation.
mdc view wave waves.mxd mdc download dsim.log
A reference design example, Gowin_I2C_Master_refDesign, has been provided for you. It can be downloaded here. It contains all the necessary files for you to simulate the design with DSim Cloud. Follow the HOW TO RUN SIMULATION instructions in Gowin_I2C_Master_RefDesign/doc/readme.txt to simulate the design with GOWIN IP.
Step 4 of the instructions says to enter this DSim Cloud command to simulate the reference design example:
mdc dsim -a '-top work.i2c_tb +acc+b -F filelist.txt -waves waves.mxd -wave-scope-specs wave.list'
Since the example is purely Verilog, the 3 stages of simulation can be executed in 1 step with the
dsim command taking the following arguments:
-top work.i2c_tb specifies the top-level module as i2c_tb in the default library work
+acc+b generates support for waveform dump at compile-time
-F filelist.txt reads options relative to the manifest file filelist.txt, ie. the files to compile
-waves waves.mxd enables waveform dump to the file waves.mxd at run-time
-wave-scope-specs wave.list specifies the file wave.list as indicating the detailed scopes (signals) to dump
See DSim Common Options for details about other arguments.