Using Libraries and Configurations
||Set default library for analyzed items|
||Specify library mapping file|
||For elaboration phase only. Specifies compiled libraries to look for cells in. Library search order defined by order -L options appear on command line|
Organizing the Design Into Libraries
DSim uses the "libmap" functionality described in section 33.3.1 of the SV-LRM.
The library map, specified with
-libmap (SystemVerilog only) contains rules that assign each analyzed module/cell to a library based on its location in the filesystem. If no rule matches, then the analyzed module is placed into the library indicated by the
-lib command line option. In the absence of any rule or
-lib, the work library will be used.
-incdir directive in the lib map is ignored, as the SV-LRM does not specify what it does. If a module appears in an included file, the top-level source file (that did the include) is used as the reference point for looking it up in the lib map.
Some simulation tools process the HDL in a two-step process: first, the HDL source code is analyzed to create one or more "design libraries". Secondly, an elaboration step creates the final simulation image from these design libraries. To ease the transition for users of these tools, the Metrics simulation system now supports this model. The DVlcom (for Verilog and SystemVerilog) and DVhcom (for VHDL) tools are first used to create the design libraries, after which DSim can be invoked.
The pre-processor and analysis related options defined for DSim also apply to DVlcom and DVhcom. DVlcom also support the same
-libmap outlined above. The
-help option from either tool will give the full list.
For example, the following will create a library A with the contents of files cell1.sv, cell2.sv and cell3.sv, and create library B with the contents of cell3b.sv.
mdc dvlcom -a 'a/cell1.sv a/cell2.sv -lib A -l first.log +define+TEST_LIMIT=50' mdc dvlcom -a 'a/cell3.sv -lib A -shared-unit-scopes -l second.log' mdc dvlcom -a 'b/cell3b.sv -lib B -timescale 1ns/1ns'
dvlcom a/cell1.sv a/cell2.sv -lib A -l first.log +define+TEST_LIMIT=50 dvlcom a/cell3.sv -lib A -shared-unit-scopes -l second.log dvlcom b/cell3b.sv -lib B -timescale 1ns/1ns
The same approach would apply to DVhcom for VHDL.
Using Configurations and Libraries
The top-level instance of a library-aware design can be specified using
If the top level is a configuration, then it can also be specified using
-top [libname.]configname. In the special case of a configuration having the same name as a cell in some library, one may specify
If you omit the optional
configname is searched according to the library search order.
The elaboration-time option
-L libname can be used to specify libraries and their search order to look for cells/configurations in. Alternatively, the libraries are searched according to the library declaration order in the library map file.
For example, if libraries tb, A and B exist in the dsim work directory, the following will elaborate and generate the design image for the top level module tb, assuming all cells required exist in the three libraries. Libraries are searched in the order tb,A,B,work.
mdc dsim -a '-top tb.top -L tb -L A -L B -genimage image'
dsim -top tb.top -L tb -L A -L B -genimage image
-libmap is specified on the command line, then DSim operates in "library-aware" mode. In this mode, if a module is added to a library and has the same name as a previously analyzed module, then the most recently analyzed module will supersede the original.
-libmap is specified on the command line, then DSim operates in "legacy" mode. In this mode, subsequent definitions of a module are ignored; the first definition wins. This is different from library-aware behavior.
You may use
-y option in "library-aware" mode. However, instead of using
-y option, it is recommended to analyze all files on the command line, use the lib map and/or DVlcom/DVhcom to organize them into libraries, and then specify configurations or -L to select cells to be instantiated in the design.