All Language Reference Manual references are noted with the following abbreviations:
- SV-LRM : SystemVerilog Language Reference Manual IEEE Std 1800™-2017(Revision of IEEE Std 1800-2012)
- VHDL-LRM : VHDL Language Reference Manual IEEE Std 1076™-2000
Beta Version: Software and results are provided as is and should be used for testing purposes only
- IEEE Std 1076™-2008
- IEEE Std 1076™-2000
Limitations with forced variables and nets
A force/release statement on singular elements (selected with a constant) of unpacked arrays is supported. However, a force/release statement on unpacked structures, unions, or elements thereof is not supported. The LHS expression of the assignment in the procedural force/release statement:
shall reference a non-random static variable or a net with a built-in net type:
- or shall be a constant indexing/field select thereof,
- or shall be a concatenation thereof
shall not involve a select operation in the LHS expansion where:
- the indexing is not constant
- the prefix type is a user-defined nettype
- the prefix type is an unpacked structure
- the prefix type is an unpacked union
- the prefix type is a dynamically sized array
shall have a singular data type:
- except entire unpacked arrays, these may be forced/released
If a forced statement (active or inactive) is applied to a net/variable or part thereof, the following accesses to that net/variable are prohibited:
- Non-singular assignment such as:
- assignment to an unpacked array slice
- Mutating array methods (e.g. sort, shuffle)
- Pass any of the following through a ref port
- the said net/variable as a whole
- a part-select of the said net/variable, even if the part-select itself is not forced
- a bit-select of the said net/variable, even if the bit-select itself is not forced
SV-LRM Reference: 10.6.2 The force and release procedural statements
Use of an unsupported SVA element will be flagged as a compile-time error.
The following properties are not currently supported:
sync_reject_on. All other property and sequence operators are supported.
Additional limitations on assertions are:
- Only variables, nets, expressions and event expressions can be passed as arguments to named sequences and properties. Arguments or local variables of type sequence or property are not yet supported.
- Recursive properties containing sample value functions, sequence methods or their own clocking event are not yet supported.
- Assertion control system tasks (section 20.12 in the SV-LRM) for ON, OFF and KILL are supported, but those related to assert action tasks are not. User may use a compile time option
-vacuousto control whether or not to execute an assertion's pass action on vacuous success.
VPI access to SVA elements (section 37) and Assertion API (section 39) are only partially supported:
- a. VPI access to assertion related objects (sections 37.47 to 37.54) is limited to concurrent and immediate assert, assume and cover statements. Access to property inst, sequence inst, property declaration, sequence declaration, property expression and sequence expression is not supported.
- b. Placing assertion system callbacks is supported only for cbAssertionSysInitialized reason.
- c. Placing assertion callbacks is supported only for reasons cbAssertionStart, cbAssertionSuccess, cbAssertionVacuousSuccess and cbAssertionFailure.
Code coverage control and API (section 40) for assertions is not supported. Coverage information for concurrent assertions and immediate cover statements are always written to the coverage database.
- A multiclocked sequence or property concatenating two possibly overlapping clock ticks may have a race condition if the ticks happen in different re-entries to the observe region during the same time step.
- An initialization assignment to local variables is not supported for properties with multiple semantic leading clocks, though an equivalent property is supported as long as the local variable initialization is done outside the local variable declaration.
- The evaluation of inout arguments to system tasks used in deferred assertion action blocks are not evaluated until the deferred time. All other input arguments, and inout arguments to non-system tasks and functions are evaluated immediately.
User may specify
-no-sva command option to ignore any concurrent assertion statement, expect property statement, property declaration, and sequence declaration.
SV-LRM Reference: 16 Assertions
Zero Delay Glitch with two Specify Blocks
Zero delay glitches may occur on a net under the influence of two specify blocks: the first specify block is inside the module instantiated in another module which contains the second specify block.
In the higher level module, a transition may be scheduled on the net in the same time slot that a zero delay change is happening in the lower level module. Due to nondeterminism in the evaluation order of these two events, the net resolved value may experience a zero delay glitch.
SV-LRM Reference: 30 Specify Blocks
General SV-LRM Support
There are several parts of the SV-LRM which are not yet supported in dsim as indicated below.
|5 Lexical Conventions||Attributes are ignored|
|7.3 Unions||Tagged unions not supported, untagged (packed and unpacked) are supported|
|10.11 Net aliasing||Feature supported but not all semantic checks are implemented.|
|11.9 Tagged union expressions and member access||Not supported|
|11.11 Operator overloading||Will never be supported; removed in 1800-2017|
|11.13 Let construct||passing event expressions not supported|
|12.4 Conditional if-else statement||Supported, with exception of matches|
|12.5 Case statement||Supported, with exception of matches.|
|12.6 Pattern matching conditional statements||Not supported|
|16.9.4 Global clocking past and future sampled value functions||Not supported|
|17 Checkers||Not supported|
|18.5 Constraint blocks||Supported. Two constraint solvers are supported: a BDD solver which produces correctly distributed results, but which does not scale to large problems, and a SAT solver which handles constraint sets too large for BDD, but which does not necessarily provide properly distributed results.|
|18.17 Random sequence generation||Not supported|
|19.3 Defining the coverage model: covergroup||Sample @@begin/end not supported|
|20.12 Assertion control system tasks||Assert controls ON, OFF and KILL are implemented for concurrent, deferred, and immediate assertions. All others are not supported|
|20.13 Sample value system functions||Global clocking past and future sample value functions not supported|
|20.14 Coverage system functions||Support functional coverage only|
|20.17 Programmable logic array (PLA) functions||Not supported|
|22.10 `celldefine and `endcelldefine||ignored|
|22.11 `pragma||Not supported, except for IEEE 1735 protection|
|23.4 Nested modules||Not supported|
|23.5 Extern modules||Not supported|
|25.6 Interfaces and specify blocks||Interface modports used as source or destination in a module path are not supported|
|25.7 Tasks/Functions||extern/forkjoin not supported, basic task/function/import/export is supported|
|31.8 Vector signals in timing checks||Vectors are supported but the option to create multiple single bit timing checks is not supported|
|32.9 Loading timing data from SDF||Supported, with the exception of a providing config file|
|33 Configuring the contents of a design||Not supported: parameter overrides|
|34 Protected envelopes||IEEE 1735 V1 is supported, V2 is not entirely. Contact Metrics for key if interested.|
|36 Programming language interface (PLI/VPI)||Rudimentary support for certain PLI libraries available|
|37 VPI object model diagrams||Rudimentary support for subset required for UVM register model backdoor. This support should be considered experimental.|
|38 VPI routine definitions||Rudimentary support for subset required for UVM register model backdoor. This support should be considered experimental.|
|39 Assertion API||Partial support|
|40 Code coverage control and API||Not Supported|
|41 Data read API||Not Supported|
VHDL 2008 support
|VHDL2008 LRM Section||Notes|
|5.3.2 Array types||Element constraints partially supported|
|5.3.3 Record types||Element constraints not supported|
|5.6 Protected types||Operator overloading for methods not supported|
|6.3 Subtype declarations||Element constraints and record element resolution not supported. Array element resolution is supported.|
|6.5 Interface declarations||Interface type/subprogram/package declarations not supported for entities.|
|6.11 PSL||Not supported.|
|9.3.6 Type conversions||Conversion between floating array and integer array not supported.|
|9.4.3 Static expressions||Entity attributes are not treated as globally static.|
|10.5 Signal assignment statement||force/release not supported.|
|11.6 Concurrent signal assignment||force/release not supported.|
|16.2 Predefined attributes||some attributes new to 2008 not supported.|
|17-23 VHPI||not supported.|
VHDL 2019 support
The conditional analysis directives are supported. No other feature new to 2019 is supported.