Compile Once, Run Multiple Times

When invoked with no special options, DSim will compile a SystemVerilog program and then immediately execute it. The SystemVerilog code is first compiled into a shared library, called the "image". The image is then loaded into memory and executed in conjuction with a run-time event scheduler.

For VHDL DSim can only combine pre-compiled libraries to generate the image.

It is often useful to compile a single image, and then use the image to run multiple tests. This can be done using the following options on DSim:

If a single image is used to run multiple tests, then different simulation outcomes can be achieved by doing one or more of the following:

• Use command-line plusarg options, and $value$plusargs to affect control flow. The UVM +UVM_TESTNAME=... is a good example of this.
• Use different random seeds, set with -sv_seed.
• Use a PLI or DPI library, which can be named using the -sv_lib or -pli_lib option. Alternatively, use LD_LIBRARY_PATH to control how a library resolves.

Selectively Enabling Top-Level Modules

Modern verification methodologies such as UVM allow the user to compile all tests cases into a single image, and then select a test at run time. An older methodology is to compile the design and testbench along with a testcase module, and then run it. A fresh compile is required to run a different test case, which can be time consuming.

As an alternative, DSim allows multiple testcase modules to be compiled alongside a common testbench and design, using a single compile. At run time, one or more of these testcase modules can be enabled.

These options work in conjunction with -top. If either -top or -compile-top is given, then:

• All modules listed after -top are unconditionally marked as top-level instances, and will always appear in the design.
• All modules listed after -compile-top are marked as run-time selectable top-level instances. These are compiled, but will appear in the design only if enabled.

If neither -top nor -compile-top is given then top-level modules are determined as required in the SV-LRM.

Anything compiled with -compile-top must still adhere to Verilog or VHDL rules:

• Modules must not have the same name as modules compiled with -top.
• Hierarchical references from hierarchy under a -top module to hierarchy under a -compile-top module are permitted, but will abort at run time unless the target hierarchy is enabled.

At run time, any module compiled with -compile-top can be "turned on" with -run-top.