Running A VHDL Simulation (Beta)

The DSim tools allow control through the three stages of a simulation.

A necessary part of any VHDL simulation in DSim is to provide the timescale during the Elaboration stage. For the purposes of these examples assume a timescale of 1ns/1ps. For more information on -timescale please refer to Common Options.

Provided IEEE Standard Libraries

If your designs will use any of the IEEE standards for VHDL, they have been provided pre-compiled for DSim and made available in the path stored in the STD_LIBS environment variable.

The included libraries are:

• ieee87
• ieee93
• ieee08

To include them in your flow you will need to use DLib to link them to your workspace (see Managing Libraries).

DSim Cloud CLI

See How To: Set up IEEE Standard Precompiled Libraries in DSim Cloud

DSim

dlib map -lib ieee ${STD_LIBS}/<library>

Building A Library

Due to the nature of VHDL, the Analyze stage MUST be performed as a separate stage. To do this the DVhcom tool can be used to parse all the files and add the resulting design components to a library that can later be used to create different types of images.

The following command will parse the given design files and populate the library (Analyze).

DSim Cloud CLI

mdc dvhcom -a '<design files> ...'

DSim

dvhcom <design files> ...

DVhcom can be run on all files together or each file independantly - depending on what command line options are necessary for each file. Design components can be added to the same library or distributed accross multiple libraries. All libraries needed for a given simulation must be located/linked into a single DSim workspace. For linking a library refer to Managing Libraries.

When a file which is being analyzed contains an external reference, the reference must be found within one of the local libraries. If that reference is to a pre-compiled library, it must already be linked (see previous section). Lowest level design components must be analyzed first. The higher level components follow. This ordering is important so that the all references are properly resolved.

The default library is work, but can be replaced with any preferable name.

The following command will elaborate a design based on a given top-level name (Elaborate) and run the simulation (Run).

DSim Cloud CLI

mdc dsim -a '-timescale 1ns/1ps -top <library>.<module name> ...'

DSim

dsim -timescale 1ns/1ps -top <library>.<module name> ...

If desired the building of the image and the running of the simulation can also be separated. See also Compile Once, Run Multiple Times.

DSim Cloud CLI

mdc dsim -a '-genimage image -top <library>.<module name> ...'

DSim

dsim -genimage image -top <library>.<module name> ...

And

DSim Cloud CLI

mdc dsim -a '-timescale 1ns/1ps -image image ...'

DSim

dsim -timescale 1ns/1ps -image image ...

The advantage of this flow is the ability to parse each design file only once in order to build a variety of designs for simulation.

For management and inspection of the design component library you can use the DLib tool as follows.

To list all libraries

DSim Cloud CLI

mdc dlib -a 'ls'

DSim

dlib ls

To list design components within a library

DSim Cloud CLI

mdc dlib -a 'ls -lib <library name>'

DSim

dlib ls -lib <library name>

For more information please refer to Managing Libraries

Mixed VHDL/Verilog Designs

This feature should be considered alpha quality.

Instantiating Verilog Inside VHDL

You must declare and instantiate a component:

// leaf.v
module leaf #(parameter W=8) (input clk, input [W-1:0] d, output reg q);
...
endmodule


-- top.vhdl
component leaf
generic(
    W: integer
);
port(
    clk: in std_logic;
    d: in std_logic_vector(W-1 downto 0);
    q: out std_logic
);
end component

u1: leaf
    generic map(
        W => 4
    )
    port map(
        clk => clk,
        d => d,
        q => q
    );

You may encounter a 3-rd party IP that doesn't adhere to the above requirement. As a workaround, try to analyze its Verilog with -gen-proto option.

To compile: you may pre-analyze the Verilog with DVLcom:

DSim Cloud CLI

mdc dvlcom -a 'leaf.v'
mdc dvhcom -a 'top.vhdl'
mdc dsim -a '-top work.top'

DSim

dvlcom leaf.v
dvhcom top.vhdl
dsim -top work.top

Alternatively, analyze all Verilog at the time of elaboration:

DSim Cloud CLI

mdc dvhcom -a 'top.vhdl'
mdc dsim -a 'leaf.v -top work.top'

DSim

dvhcom top.vhdl
dsim leaf.v -top work.top

You cannot instantiate a Verilog object directly as a VHDL entity. You may reference a Verilog object as a VHDL entity in a component configuration or configuration specification. However, incremental binding (both port map and generic map) are not supported.

Instantiating VHDL Inside Verilog

You may refer to a VHDL item using the full library path as a Verilog extended name:

-- leaf.vhdl
entity leaf is
generic(
    W : integer
);
port(
    clk: in std_logic;
    d: in std_logic_vector(W-1 downto 0);
    q: out std_logic
);
end leaf;


// top.sv
\work.leaf #(4) dut(
    .clk(clk),
    .d(d),
    .q(q));

The VHDL items must be analyzed with DVhcom, after which the Verilog can be compiled and elaborated:

DSim Cloud CLI

mdc dvhcom -a 'leaf.vhdl'
mdc dsim -a 'top.sv -lib work'

DSim

dvhcom leaf.vhdl
dsim top.sv -lib work

Binding Verilog Items Into a VHDL Design

A Verilog item can be bound into a VHDL design. The syntax is identical to binding a Verilog item into a Verilog design.

Supported Type Conversions

The following data type conversions are supported for generic/parameter mapping and port connections:

A VHDL string may be mapped to an untyped Verilog parameter, in which case the reg[n*8-1:0] representation will be used on the Verilog side.