The User Guide: DSim Major Release Highlights article outlines the high-level functionality of the 20220328. This article outlines the contents of each of the minor releases that have been deployed since the 20220328 Major release.
RELEASE: 20220328.16.0
Summary
- 4 Bugs fixed
- 1 HIGH Severity
- 3 MEDIUM Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B237 |
Internal DSim bug (user not affected) |
MEDIUM |
| B392 |
InvalidAggNames error in encrypted IP block from FPGA vendor library |
HIGH |
| B415 |
Interface class compliance checker must consider superclasses |
MEDIUM |
| B424 |
Internal DSim bug (user not affected) |
MEDIUM |
RELEASE: 20220328.15.0
Summary
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B95 |
Internal bug for improving memory utilization |
MEDIUM |
| B388 |
Wrong value of VHDL pre-defined 'last_active attribute when used inside a procedure function |
MEDIUM |
| B423 |
Internal DSim bug (user not affected) |
MEDIUM |
RELEASE: 20220328.14.0
Summary
- 6 Bugs fixed
- 1 HOTFIX Severity
- 5 MEDIUM Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B369 |
Unexpected behavior when trying to use 'last_value' attribute in a proc function |
MEDIUM |
| B389 |
Enhanced the handling of a class specialization declared in an interface. Enhanced the handling of a mailbox message in cases where the get() method blocks a calling process, which is getting disabled. |
HOTFIX |
| B410 |
Synchronous driving of signal within clocking block is incorrectly deferred to the next clocking event - scenario1 |
MEDIUM |
| B411 |
Synchronous driving of signal within clocking block is incorrectly deferred to the next clocking event - scenario2 |
MEDIUM |
| B414 |
Fix for assignment propagation endless loop during compilation |
MEDIUM |
| B416 |
SV Improved fork-join semantic checking |
MEDIUM |
RELEASE: 20220328.13.0
Summary
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B376 |
DSim compilation error on undefined identifiers errors in FPGA Vendor encrypted libraries |
MEDIUM |
| B405 |
VHDL drivers not created for empty range signals |
MEDIUM |
| B407 |
Internal DSim improvement |
MEDIUM |
| B408 |
Fixed error during elaboration when encountering properties and sequences in design. |
MEDIUM |
| B419 |
Internal regression bug resolved |
MEDIUM |
RELEASE: 20220328.12.0
Summary
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B98 |
Improper dereference for transaction handle on collapsed inout leads to DSim NULL reference handle |
MEDIUM |
| B259 |
Support for Aliases VHDL |
MEDIUM |
| B265 |
Fixed an issue with Aliases VHDL |
MEDIUM |
| B398 |
Dangling generic reference in LHS leads to DSim elaboration crash |
MEDIUM |
| B404 |
Improved dvhcoms ability to detect direct writes to signals w/o using borrowed drivers |
MEDIUM |
RELEASE: 20220328.11.0
Summary
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B43 |
Improve glitch detection and correction with -opt-comb-glitch option |
MEDIUM |
| B384 |
DSim does not emit "simulation terminated" messaging when iteration limit (currently 1000000) is exceeded |
MEDIUM |
| B385 |
VHDL case-generate must use predefined operators for compare |
MEDIUM |
| B391 |
Writing to a VHDL signal through an external name reference does not update its signal attributes properly |
MEDIUM |
RELEASE: 20220328.10.0
Summary
- 3 Bugs fixed
- 1 HOTFIX Severity
- 1 HIGH Severity
- 1 MEDIUM Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B357 |
Values of external names not being done properly for all instances. |
MEDIUM |
| B378 |
Randomization cross-check failure |
HOTFIX |
| B382 |
DSim issue handling constraints referencing elements of an array within a structure. |
HIGH |
RELEASE: 20220328.9.0
Summary
- 2 Bugs fixed
- 1 HIGH Severity
- 1 MEDIUM Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B375 |
Crash in DSim when using the wait statement to wait for a change in any element of an array (e.g. wait on array) |
HIGH |
| B381 |
Correction in user manual wrt -noopt option |
MEDIUM |
RELEASE: 20220328.8.0
Summary
- 5 Bugs fixed
- 2 HIGH Severity
- 4 MEDIUM Severity
- 1 LOW Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B310 |
VHDL analysis issue related to LRM2008 12.5c) |
MEDIUM |
| B343 |
DSim silently converts string inputs to -sv_seed to integers with the value 0 |
LOW |
| B347 |
DSim Cloud limits the RAM on the remote compute to 4G, causing some customer simulations to fail (out of memory) |
HIGH |
| B372 |
DSim crash given an architecture name as a prefix to an attribute |
HIGH |
| B373 |
Error in ?<= operator given - values. |
MEDIUM |
DSim 20220328.7.0 Release
Summary:
- 7 Bugs fixed
- 6 MEDIUM Severity
- 1 LOW Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B351 |
Handle \ in macro definition |
MEDIUM |
| B350 |
Resolve modules when module name begins with \ |
MEDIUM |
| B312 |
VHDL improved error reporting when the division of two physical types returns universal_integer |
LOW |
| B346 |
VHDL 2008 to_string of real now returns real value |
MEDIUM |
| B302 |
Improved error messages of accelerated numeric_std |
MEDIUM |
| B338 |
Fixed handling of numeric_bit ?= operator |
MEDIUM |
| B314 |
Accelerated version numeric_std handles null ranges |
MEDIUM |
DSim 20220328.6.0 Release
Summary:
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B352 |
Fixed input port signal updating when run with -noopt |
MEDIUM |
| B348 |
Optimization of 1-3 input combinational UDP's when some inputs are constants. |
MEDIUM |
DSim 20220328.5.0 Release
Summary:
- 4 Bugs fixed
- 1 HIGH Severity
- 2 MEDIUM Severity
- 1 LOW Severity
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B311 |
Improved type handling of $cast() and error reporting |
HIGH |
| B290 |
Fixed name collision (port/instance) in config port map |
MEDIUM |
| B341 |
Compilation messages around incorrect $sformatf() usage are unclear |
MEDIUM |
| B343 |
DSim silently converts string inputs to -sv_seed to integers with value 0 |
LOW |
DSim 20220328.4.0 Release
Summary:
- 1 Feature(s) Included
- 2 Bugs fixed
Features Included
| ID |
Release Note |
| SS41 |
VHDL2008 support for cascading if-else clauses for if-generate, as well as a case-generate |
Bug Fixes Included:
| ID |
Release Note |
Severity |
| B313 |
Adding +acc+f sets up all variables for potentially being forced from VPI. This caused assignment to unpacked elements to be incorrectly handled. |
MEDIUM |
| B342 |
Ordering of if condition terms within an always @(*) can lead to unexpected results when one of those terms is provably a constant 0 or a constant 1. |
MEDIUM |
