How To: Simulate a Design with Vivado IP
Introduction
This How To guide is intended to be used by Xilinx customers to simulate their FPGA designs with Vivado IP via Metrics DSim Cloud. It provides a generic procedure that can be applied to all such designs. The procedure gives recommended best practices without limiting the user's flexibility on workflow.
Contents
Prerequisites
Vivado
- Have a working installation of Xilinx Vivado ML on your local machine.
- Successfully compile your design in Vivado ML.
DSim Cloud
- Complete the DSim Cloud Tutorial.
- Understand how to run a simulation in DSim - Verilog and/or VHDL, as applicable to your design.
- Review considerations for choosing the DSim Cloud local workspace.
- Understand how to use libraries in DSim.
- Understand how to use DSim Cloud CLI Tool simulator commands.
Procedure
1. Prepare your local workspace
Ensure that all files needed to simulate your design are under your local workspace. These files include all design, testbench, memory initialization, and source code for generated IP blocks. For the purpose of this guide, we will call this local workspace <my_project>.
Create a folder under <my_project> called <mdc> where you will simulate your design with DSim Cloud. For example, you can create it as <my_project>/simulation/mdc. Copy all your memory initialization files (*.mif) to this folder. *mif files are not compiled but must reside in the same folder where you run your DSim Cloud simulation. You will also need a copy of glbl.v, which can be found in <my_project>/my_project.sim/sim_1/behav/xsim/.
If any source code for an IP block is encrypted, you must provide the file encrypted for Metrics.
To use any of the IP encrypted for Metrics, you will have to either copy the files from the Vivado installation directory into your local workspace and reference them from there, or use the files from the DSim Cloud by referencing them using the VIVADO_HOME environment variable. See Vivado FPGA HDL Library Package for more information.
2. Create a compile list
For all the files required for compilation and simulation, you must know their language type, the library into which they should be compiled, and their source file location. For VHDL files, the order of compilation must be known. If desired, you can create a list of all files needed to compile and simulate the design, to keep track of this information. For example, under <my_project>:
| Order | file_name | Type* | library_name | path |
|---|---|---|---|---|
| 1 | fifo_generated.v | Verilog | sim_lib | /ip/sim/ |
| 2 | my_block.vhd | VHDL | design_lib | /src/hdl/ |
| 3 | my_unencrypted_ip.v | Verilog | ip_lib | /ip/sim/ |
| 4 | encrypted_ip_1.v | Verilog | ip_lib | /ip/sim/ |
| 5 | encrypted_ip_2.vhd** | VHDL | ip_lib | %VIVADO_HOME%/data/../.. /encrypted_ip_2.vhd |
| 6 | my_dut.vhd | VHDL-2008 | xil_defaultlib | /src/hdl/ |
| 7 | my_tb.sv | SV | test_lib | /src/tb/ |
| 8 | glbl.v | Verilog | sim_lib | /src/ |
*VHDL = VHDL-1993 unless otherwise noted
**this file is not in your local workspace, but is being referenced from the DSim Cloud Vivado FPGA HDL Library Package
A compile list may be easily generated in Vivado by doing the following:
1. Run Behavioral Simulation.
2. Enter this command in the Tcl Console command field:
report_compile_order -used_in simulation
3. Copy the table from the resulting Tcl Console output into the compile list.
4. Add glbl.v to the compile list.
3. Create a compile script or list of DSim Cloud commands
There are many ways to compile and simulate your design with the DSim simulator, contained within the DSim Cloud platform. Basically, you need to wrap the DSim command options to analyze, elaborate, and run your design, in single quotes so that the DSim command is executed on the remote compute.
Both IP and design files must be compiled into the appropriate libraries with DSim Cloud commands. The commands are different for Verilog / SystemVerilog files and VHDL files.
Verilog / SystemVerilog
mdc dvlcom -a '-lib <library_name> <path>/<file_name>.v'
For example:
mdc dvlcom -a '-lib sim_lib ./src/glbl.v' mdc dvlcom -a '-lib ip_lib -F ip_filelist.txt'
VHDL
mdc dvhcom -a '-vhdl93 -lib <library_name> <path>/<file_name>.vhd'
For example:
mdc dvhcom -a '-vhdl2008 -lib xil_defaultlib ./src/hdl/my_dut.vhd'
Depending on the complexity of your design, and your familiarity with scripting, you can put all these DSim Cloud commands together in a compile script and run the script with DSim Cloud. The script runs on your local compute and makes calls to DSim through the DSim Cloud CLI.
4. Simulate your design in DSim Cloud
1. Initialize a DSim Cloud workspace in your local workspace <my_project> from section 1 of the Procedure.
mdc initialize
2. Navigate to the <my_project>/simulation/mdc folder where you will run your simulation.
3. Set up the Xilinx Vivado precompiled libraries in DSim Cloud.
4. Compile all the files into their appropriate libraries using the methods in section 3.
5. Elaborate your design. For example:
mdc dsim -a '-genimage image -top test_lib.my_tb -top sim_lib.glbl +acc+b'
6. Run your design. For example:
mdc dsim -a '-image image -waves waves.mxd -wave-scope-specs wave.list'
7. You can view waveforms and/or download the DSim log to debug your simulation.
mdc view wave waves.mxd mdc download dsim.log