How To: Simulate the Vivado Reference Design

Introduction

This How To guide is intended to be used by Xilinx customers to simulate the Vivado Reference Design "wavegen" with Metrics DSim Cloud.

Contents

1. Prerequisites
2. Procedure
   1. Generate the "wavegen" design
   2. Compile the "wavegen" design with Vivado Simulator
   3. Simulate the "wavegen" design with DSim Cloud

Prerequisites

Vivado

1. Have a working installation of Xilinx Vivado ML on your local machine.

DSim Cloud

1. Complete the DSim Cloud Tutorial.

Procedure

1. Generate the "wavegen" design

1. Start Vivado ML and click on Open Example Project.

2. Click Next.

3. Scroll down the Templates to select Wavegen (HDL) and click Next .

4. Enter wavegen for the Project name and click Next .

5. Select xc7k70tfbg676-1 as the Default Part and click Next .

6. Ensure the project summary matches the screenshot below and click Finish .

2. Compile the "wavegen" design with Vivado Simulator

1. Under SIMULATION of the Flow Navigator , right-click Run Simulation and select Simulation Settings...

2. Under Project Settings , select Simulation . Under Simulation, select the Simulation tab and change xsim.simulate.runtime to 1000us . Ensure the other settings match the screenshot below and click OK .

3. Under SIMULATION of the Flow Navigator , click Run Simulation and select Run Behavioral Simulation.

4. Verify that the simulation output in the Tcl Console window looks like the output below. If not, contact Xilinx Support to properly generate and simulate the "wavegen" design.

 # run 1000us   
 WARNING: Behavioral models for independent clock FIFO configurations do not  
model synchronization delays. The behavioral models are functionally correct,  
and will represent the behavior of the configured FIFO. See the FIFO  
Generator User Guide for more information.   
  10.00 ns    Starting simulation   
  10.00 ns    Writing 0001 to RAM location 0   
  10.00 ns    Writing 0020 to RAM location 1   
  10.00 ns    Writing 0001 to RAM location 2   
  10.00 ns    Asserting reset for    4000 clocks   
  20007.50 ns    Deasserting reset   
  220007.50 ns    Writing 0004 to RAM location 0   
 220007.50 ns    Sending cmd =  *N0004, expecting rsp =       -OK   
  220007.50 ns    Sending character 2a (*)   
  306817.50 ns    Sending character 4e (N)   
  377499.78 ns    Character received 2a (*)   
  393627.50 ns    Sending character 30 (0)   
  464439.78 ns    Character received 4e (N)   
  480437.50 ns    Sending character 30 (0)   
  551379.78 ns    Character received 30 (0)   
  567247.50 ns    Sending character 30 (0)   
  638319.78 ns    Character received 30 (0)   
  654057.50 ns    Sending character 34 (4)   
  724719.78 ns    Character received 30 (0)   
  812199.78 ns    Character received 34 (4)   
  898599.78 ns    Character received 2d (-)   
 984999.78 ns    Character received 4f (O)

5. In the Waveform window, click Zoom Fit and verify that the simulation waveforms look like the waveforms below. If not, contact Xilinx Support to properly generate and simulate the "wavegen" design.

3. Simulate the "wavegen" design with DSim Cloud

1. Create a folder called mdc under the example project folder /wavegen/wavegen.sim/sim_1/behav and extract the contents of mdc-sim-wavegen-main.zip into it.

2. From your terminal window, initialize a DSim Cloud workspace in /wavegen/:

 mdc initialize

3. Change your mdc_config.yml to Set up Xilinx Vivado Precompiled Libraries.

4. Navigate to the simulation folder by entering:

 cd wavegen.sim/sim_1/behav/mdc

5. In Windows, simulate the "wavegen" design by entering:

 .\run_mdc.ps1

6. In Linux or Mac, simulate the "wavegen" design by entering:

sh run_mdc.sh

7. Download dsim.log by entering:

mdc download dsim.log

and verify that the output matches the output from the Vivado Tcl Console.

8. View the waveform by entering:

mdc view wave waves.mxd

and verify that the waveforms resemble the waveforms from Vivado.

10. Examine /wavegen/wavegen.sim/sim_1/behav/mdc/run_mdc.sh to understand the commands Metrics DSim Cloud uses to compile and simulate the "wavegen" design.