DSim Cloud comes with the Intel Quartus standard libraries, both Verilog and VHDL, precompiled. The following are the precompiled standard libraries:
To use the Quartus precompiled libraries in your DSim simulations, you need to map them as follows:
1. Within an initialized DSim Cloud workspace, modify and save the configuration file config.yml for the appropriate VHDL library. To see how to change your config.yml, see DSim Cloud Configuration.
2a. To map the Quartus libraries with the VHDL IEEE-1993 library, uncomment the entry for the Quartus package in your config.yml:
- name: quartus
2b. To map the Quartus libraries with the VHDL IEEE-2008 library, change the version field of the IEEE library to "08" and uncomment the entry for the Quartus package in your config.yml:
- name: ieee
- name: quartus
3. For every Verilog library component required in your design, ensure to add it to your DSim command:
dsim -L <lib_ver>
mdc dsim -a '-F filelist.txt -L altera_ver -L lpm_ver -L sgate_ver +acc+b -waves waves.vcd'
To see what libraries are mapped in your work directory, enter:
mdc dlib -a 'ls'
To see the components inside a particular library, like mylib, enter:
mdc dlib -a 'ls -lib mylib'
You can try out the above Procedure with a provided example design as follows:
1. Download example_quartus-main.zip
2. Extract the contents of this file into a folder called example_quartus-main
3. Open a terminal window and navigate to example_quartus-main:
4. Initialize a DSim Cloud workspace:
5. Navigate to SystemVerilog/sim:
6. Compile and run the simulation:
mdc dsim -a '-F filelist.txt -L lpm_ver +acc+b -waves waves.vcd'
To get a better understanding of how to use DSim Cloud for mixed language simulations, open readme.txt under the /sim folder of the appropriate language (SystemVerilog / VHDL / VHDL_SystemVerilog).