This How To guide is intended to be used by Intel customers to simulate the Quartus Reference Design "Turbo-V" with Metrics DSim Cloud.
- Have a working installation of Quartus Prime 22.2 Standard or Pro on your local machine.
- Install Intel® Arria® 10 device support.
- Complete the DSim Cloud Tutorial.
1. Generate the "Turbo-V" design
- Create a folder on your local computer called turbo_v.
- Start Quartus Prime.
- Create a New Quartus Prime Project by clicking File -> New -> OK.
- Select turbo_v as the working Directory, Name, and Top-Level Entity for this project and click Next.
- Select Empty project in the Project Type window and click Next.
- Click Next in the Add Files window.
- Select Arria 10 (GX/SX/GT) from the Family drop-down menu and Arria 10 GT from the Device drop-down menu. Select the 10AT115S1F45E1SG as the device and click Next.
- Click Next in the EDA Tool Settings window.
- Verify that the Summary window looks like this (path of Project directory may vary) and click Finish.
- Open the IP Catalog and select DSP -> Error Detection and Correction -> 4G Turbo-V Intel FPGA IP and click Add.
- Enter my_turbov for your New IP Variant and click Create.
- Choose Uplink and click Generate Example Design.
- Select the example design directory as /turbo_v/intel_FPGA_turbov_0_example_design and click OK.
- A window confirming the successful generation of the design should appear after a few minutes. If not, contact Intel FPGA Support to properly generate the “4G Turbo-V” example design. Click Close.
- Close the IP Parameter Editor Pro window. When asked to save changes, click Don’t Save.
2. Simulate the "Turbo-V" design with DSim Cloud
- Create a folder called mdc under the example project folder /turbo_v/intel_FPGA_turbov_0_example_design/simulation_scripts/ and extract the contents of the attached file mdc.zip into it.
- From your terminal window, initialize a DSim Cloud workspace in /turbo_v/intel_FPGA_turbov_0_example_design/:
- Change your config.yml to Set up Intel Quartus Precompiled Libraries.
- Navigate to the simulation folder by entering:
- In Windows, simulate the "Turbo-V" design by entering:
- In Linux or Mac, simulate the "Turbo-V" design by entering:
- The design will take several minutes to compile and run, after which you can download dsim.log by entering:
mdc download dsim.log
and verify that the end of the output looks like this:
Inputting TC = 10
Inputting TC = 11
Outputting TC = 9 (PASS)
Outputting TC = 10 (PASS)
Outputting TC = 11 (PASS)
=T:Simulation terminated by $finish at time 207575000 (../../src/turbov_ul_top_tb.sv:299);
- Examine /turbo_v_0/intel_FPGA_turbov_0_example_design/simulation_scripts/mdc/run_mdc.sh to understand the commands Metrics DSim Cloud uses to compile and simulate the "Turbo-V design.