Simulator (DSim)
Common questions, tips on - DSim usages - HDL Language: SystemVerilog, Verilog, VHDL - Methodology: UVM, OVM, VMM
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How To: Integrate C/C++ Files with Your Design
Given a C file my_project/src/my_dpi_code.c or C++ file my_project/src/my_dpi_code.cpp, you can i... -
How To: Simulate Mixed Language Designs
DSim Cloud fully supports mixed language designs in VHDL, Verilog, and SystemVerilog. There are d... -
How To: Debug a Hung Simulation
There are several possibilities: Your code is stuck in an endless loop. Events are not being pro... -
How To: Use UVM in a Simulation
1. Load the desired UVM package. 2. Include uvm_macros.svh and import the UVM package in all yo... -
How to: Enable Waveform Dumping
DSim supports VCD waveform dump to a file. When you want to dump waveforms during your simulation...